The present invention relates to the technology for synthesizing a layout module for a data path circuit used in an LSI including a CMOS.
In recent years, a degree of integration and a clock frequency of an LSI have been increased continuously. According to current estimates the number of transistors per unit area of 1 cm.sup.2 in an LSI will reach 18 millions in 2003, while the clock frequency used therein will be as high as 500 MHz (ASP-DAC '98, Tutorial 3, "Analysis/Optimization of Performance and Noise in Deep Submicron Designs," Tuesday, Feb. 10, 1998).
Under such circumstances, LSI manufacturing has entered a deep submicron era and LSI design has become increasingly complicated. For example, since the wiring spacing has been minimized to approximately 0.1 .mu.m, delay and power consumption are more dependent on wiring load than on gate capacitance. Thus, it has become extremely difficult to evaluate the delay, power consumption, and clock skew of an LSI in the upper process of design (functional level and RTL level). The minimized wiring spacing also requires a wiring model, used for estimating a wiring delay, to reflect the influence of the coupling capacitance of wires. However, it is substantially impossible to estimate the coupling capacitance of wires in the upper process of design.
Consequently, the capability to correct the result of the upper process of design in the lower process of design (logic level and transistor level) becomes extremely important. By establishing a close linkage between the evaluating capability in the upper process of design and the correcting capability in the lower process of design, iteration in the LSI design can be lessened, which reduces design cost and implements higher-quality LSI design.
To establish a close linkage between the upper and lower processes of design, it is necessary to provide, from the lower side of design, accurate data about the performance and area of a module required by the upper side of design in a shorter period of time. In short, a module synthesizing apparatus used in the lower process of design should have a capability of instantaneously estimating the results of syntheses with respect to a plurality of conditions in order that a tool for synthesis used in the upper process of design can explore a design space for optimizing module allocation and binding. However, the conventional module synthesizing apparatus does not have such a capability and merely synthesizes a layout module with respect to a single condition. If the performance and area of a module are to be estimated with respect to a plurality of conditions, therefore, the conventional module synthesizing apparatus has no other alternative than to actually synthesize the module with respect to each of the conditions, which wastes a great deal of processing time.
In addition, since a cell used in the conventional module synthesizing apparatus has substantially no geometrical flexibility, a dead area is likely to arise when a cell having an optimum driving ability is selected. As a result, the geometry of a layout module cannot be optimized with accuracy.